1. Field of the Invention
The present invention relates to a high-definition television receiver, and more particularly, to a demodulating system for a high-definition (HD) television receiver.
2. Discussion of Related Art
In the vestigial side band (VSB) system which is selected for the United States HD television transmission system format, a frequency and phase locked loop (FPLL) is used for the synchronization of the carrier.
The FPLL recovers the frequency and phase of a carrier selected by a tuner out of a plurality of radio frequency (RF) signals received via an antenna. The carrier recovered by the FPLL is used as a loop-controlling signal for converting the RF signals received by the tuner into signals of a low band.
FIG. 1 is a block diagram of an HDTV demodulating system used by America's Zenith Co., Ltd. The system comprises a tuning circuit 10 for selecting one out of a plurality of RF signals and converting the selected carrier into an intermediate frequency signal according to an input loop-controlling signal, an oscillating circuit 20 for generating a sine signal, and a FPLL 30 for sending the loop-controlling signal for synchronizing the phase and frequency of the intermediate frequency signal including the carrier selected to the tuning circuit 10, using an algorithm to determine the phase and frequency of the sine wave output from the oscillating circuit 20, and outputting this information from the tuning circuit 10.
In FIG. 1, tuning circuit 10 includes an antenna 10a for receiving a plurality of RF signals, a double conversion tuner 10b, a channel selector 10c, serving as a first oscillator for selecting, according to a user's selection, one of the RF signals received by the double conversion tuner 10b, and converting the selected carrier into a first intermediate frequency signal. A voltage controlled oscillator (VCO) 10d, serving as a second oscillator for converting the first intermediate frequency signal into a second intermediate frequency signal with a frequency band within a reasonable range for a general circuit is also included. Further, a SAW filter 10e for filtering the second intermediate frequency signal output via the double conversion tuner 10b is included along with an amplifier 10f for amplifying the second intermediate frequency signal output from the SAW filter 10e.
FPLL 30 comprises a phase shifter 30a for shifting the phase of the sine wave output from the oscillating circuit 20 by a predetermined angle (here, 90.degree.); a multiplier 30b for multiplying the second intermediate frequency signal, output from the tuning circuit 10, by the output signal of the phase shifter 30a and outputting the product as an I-channel beat signal; a multiplier 30c for multiplying the sine wave signal output from the oscillating circuit 20 by the second intermediate frequency signal output from the tuning circuit 10 and outputting the product as a Q-channel beat signal; an automatic filtering control (AFC) low-pass filter 30d for passing only a predetermined low band of a signal out of the I-channel beat signal and changing the phase of the signal according to the frequency of the I-channel beat signal; a limiter 30e for amplifying and limiting the output signal of the AFC low-pass filter 30d to a predetermined amplification degree; a multiplier 30f for multiplying the output signal of multiplier 30c by the output signal of the limiter 30e; and an automatic phase control (APC) low-pass filter 30g for passing only a predetermined low frequency band of signal out of the output signal of multiplier 30f and providing the passed signal to VCO 10d of tuning circuit 10, as a loop-controlling signal for correcting the frequency of a selected carrier.
In FIG. 1, FPLL 30 may further comprise an analog-to-digital (A/D) converter 30h for converting the I-channel signal output from the I-channel multiplier 30b into a digital signal and sending it to another channel block.
The operation of the demodulating system of FIG. 1 will be described. Out of a plurality of RF signals received via antenna 10a, one carrier is selected by the channel selector 10c in the double conversion tuner 10b and converted into a first intermediate frequency (IF) signal.
The first IF signal is designed to fall within a frequency band which does not interfere with other RF channel signals. The first IF signal is converted into a second IF signal by the second oscillator, VCO 10d, via an amplifier and a band-pass filter (not shown) of the double conversion tuner 10b.
The second IF frequency signal has a frequency band within a reasonable range for a general circuit and the signal does not interfere with other RF channel signals, even though the signal is greatly amplified and filtered.
The IF frequency band is used because, in detecting the RF signal as a low-band signal, there is reduced distortion to the video signal, as compared to using a RF signal directly converted into a low-band signal or using a RF signal that is first converted into an IF signal, filtered and amplified, and then converted into the low-band signal.
The second IF signal output from the double conversion tuner 10b is converted into an appropriate form by the SAW filter 10e and the IF amplifier 10f. The IF signal carrier is multiplied by the sine wave output from the final oscillator, oscillating circuit 20, in multipliers 30b and 30c of the FPLL 30, and then converted into a low-band signal.
FPLL 30 generates two channel signals, an I-channel signal and a Q-channel signal. They have a predetermined phase difference (here, 90.degree.).
The I-channel signal out of the low-band signals is digitalized by the A/D converter 30h and output to another channel block for video data detection.
In order for the I-channel signal to conform to the low-band signal sent from a broadcasting station, the frequency and phase of the sine wave output from the HDTV oscillator 20 must coincide precisely with the frequency and phase of the final signal of the IF signal carrier selected and output from the tuning circuit 10. One way to properly adjust the frequency and phase is to first set one of the signals between the sine wave of the oscillating circuit 20 and the IF signal carrier, and then set the other signal.
The system of FIG. 1 sets the oscillating circuit 20 signal as a reference oscillator and the frequency and phase of the IF signal carrier is changed to match. In order to change the frequency and phase of the final IF signal carrier, the oscillating frequency of VCO 10d, which forms the second IF signal, is altered.
The direction and magnitude of the oscillating frequency of VCO 10d is obtained by operating the FPLL in accordance with an algorithm for generating the I-channel signal and Q-channel signal, which are both low-band signals. The purpose of the FPLL 30 is to determine the direction and magnitude of frequency signals. The operation of FPLL 30 will be described below.
If the frequency of the final IF carrier signal is not the same as that of the sine wave output from the oscillating circuit 20, a beat, corresponding to the difference between the two frequencies, is large at a low band.
The sine wave of oscillating circuit 20 has a phase difference of 90.degree. in I-channel multiplier 30b and Q-channel multiplier 30c according to the phase shifter 30a, and multiplied by the final IF signal. As a result, the I-channel beat signal and the Q-channel beat signal have a phase difference of 90.degree.. For the discussion below, assume the Q-channel beat signal is a waveform as shown at the top of FIGS. 2A, 2B and 2C.
The I-channel beat signal passes the AFC low-pass filter 30d having the circuit configuration of FIG. 3A and the characteristics of FIG. 3B. The AFC low-pass filter functions to change the phase of the signal according to the frequency of the I-channel beat signal.
As shown in FIG. 3B, if the I-channel beat signal has a frequency f.sub.1, its phase is shifted by 90.degree..
When the output signal of AFC low-pass filter 30 is amplified and passed through the limiter 30e, its waveforms correspond to those in the middle of FIGS. 2A, 2B and 2C.
Multiplier 30f of FPLL 30 multiplies the waveforms at the top of FIGS. 2A, 2B and 2C and the waveforms in the middle thereof, to output the waveforms shown at the bottom of FIGS. 2A, 2B and 2C.
The signals output from multiplier 30f are input to VCO 20 10d of the tuning circuit 10 through the APC low-pass filter 30g, to correct the signals oscillating frequencies to the intended frequencies. The output signal of the APC low-pass filter 30g corresponding to the waveforms at the bottom of FIGS. 2A, 2B and 2C is the output signal of FPLL 30 and called a loop-controlling signal.
Given that the frequency of the sine wave output from the oscillating circuit 20 is F.sub.0 and the frequency of the final IF signal carrier of the selected carrier is f.sub.0. FIG. 2A shows waveforms for when f.sub.0 &lt;F.sub.0. FIG. 2B shows waveforms for when f.sub.0 .congruent.F.sub.0. FIG. 2C shows waveforms for when f.sub.0 &gt;F.sub.0.
FPLL 30 will be explained in more detail. If f.sub.0 and F.sub.0 are approximate values and the frequency f.sub.1 of the I-channel beat signal is very low, the phase shift of the signal output from AFC low-pass filter 30d is very small. Therefore, the I-channel beat signal and Q-channel beat signal maintain a phase difference of 90.degree. as in the initial state. Multiplier 30f multiplies the Q-channel beat signal by the limited I-channel beat signal and provides the FPLL output signal whose average is "0" as the loop-controlling signal as shown in FIG. 2A.
If F.sub.0 -f.sub.0 =f.sub.1 and does not equal zero, then in a frequency synchronization process, the phase shifts in the positive direction in proportion to the frequency difference f.sub.1 in AFC low-pass filter 30d. Here, the FPLL output signal is the same as FIG. 2A.
If F.sub.0 -f.sub.0 =f.sub.l and does not equal zero, then in another frequency synchronization process, the phase shifts in the negative direction are in proportion to frequency difference f.sub.1. The output signal of FPLL 30 is as shown in FIG. 2C.
As a result, the FPLL output draws a "S" curve as shown in FIG. 4 according to the frequency variation of the I-channel beat signal. The central point of the "S" curve is F.sub.0 =f.sub.0.
If F.sub.0 and f.sub.0 have the same frequencies but different phases, in the phase synchronization process shown in FIG. 5, the limited I-channel beat signal maintains value "1" and the Q-channel beat signal has a value proportional to the magnitude of the phase difference .theta..
The Q-channel-loop of FIG. 1 has the same characteristic as a general PLL loop and acts to reduce the phase difference .theta..
The output signal of FPLL 30 converges to "0" as shown in FIG. 5. FPLL 30 of the demodulating system of FIG. 1 uses the beat signals of the sine wave of the oscillating circuit 20, and the selected carrier, to extract a loop-controlling signal for synchronizing the frequency and phase of the carrier and reference sine wave. However, the IF signal contains general information data as well as the carrier, and it is difficult to extract clear I-channel beat signals and Q-channel beat signals as shown in the waveforms at the top of FIGS. 2A, 2B and 2C.
HDTV broadcasting is standardized to simulcast with the conventional NTSC broadcasting. If there is an interference of a NTSC broadcasting signal, which commonly uses the HDTV broadcasting channel, as shown in FIG. 6, a NTSC video carrier, as an interference wave, generates beat signals with the sine wave signal output from the oscillating circuit 20, similar to the carrier of an intended HDTV channel. In this case, the FPLL 30, which has the function of synchronizing the frequency and phase, is unable to perform the synchronization of the carrier of the HDTV channel.
In order to preclude the interference of the NTSC video carrier, America's Zenith Co. proposed an HDTV demodulating system as shown in FIG. 7.
This demodulating system is similar but partly different from the system of FIG. 1.
The portion of the demodulating system of FIG. 7 similar to FIG. 1 comprises the tuning circuit 10, the oscillating circuit 20 and the FPLL 30. This demodulating system further comprises two identical blocks 30A and 30B added to the I channel and the Q channel of FPLL 30 in order to remove the NTSC video carrier.
Block 30A is inserted between I-channel multiplier 30b and AFC low-pass filter 30d, whereas block 30B is inserted between Q-channel multiplier 30c and multiplier 30f.
Block 30A comprises an A/D converter 30i for converting a beat signal into a digital signal, an NTSC removing filter 30j for removing the NTSC video carrier, shown in FIG. 6, out of the output signals of the A/D converter 30i, and a D/A converter 30k for converting the output signal of the NTSC removing filter 30j into an analog signal.
Block 30B removes the NTSC video carrier in the Q channel and also includes an A/D converter 30l, an NTSC removing filter 30m and a D/A converter 30n.
NTSC removing filters 30j and 30m, as is well-known in the art, are digital comb filters. For this reason, in order to operate the NTSC removing filters 30j and 30m, A/D converters 30i and 30l for digitalizing the I-channel beat signal and the Q-channel beat signal are coupled to the input of the filters. D/A converters 30k and 30n are connected to the output of the NTSC removing filters 30j and 30m in order to process the I-channel beat signal and the Q-channel beat signal, from which the NTSC video carrier is removed, using an analog signal.
In the configuration of FIG. 7, in order to remove the interference of the NTSC video carrier and improve the performance of the FPLL 30, digital processing portions such as a D/A converter and an A/D converter are added in the FPLL, resulting in complicated hardware. Further, this configuration increases the probability that digital noise will be output as analog noise.